It is often necessary in semiconductor processing to fill a high aspect ratio gap with insulating material. As device dimensions shrink and thermal budgets are reduced, void-free filling of high aspect ratio spaces (AR>3.0:1) becomes increasingly difficult due to limitations of existing deposition processes. The deposition of doped or undoped silicon dioxide assisted by high density plasma CVD, a directional (bottom-up) CVD process, is the method currently used for high aspect ratio (AR) gap fill. The method deposits more material at the bottom of a high aspect ratio structure than on its sidewalls. HDP CVD is a line-of-sight process since it operates at a pressure regime, where the mean free path of the species is far longer than the characteristic dimension of the trenches and the thickness of the plasma sheath. Overhang at the entry region of the trenches is a generic feature of HDP CVD processes, associated with sputter etch reaction and redeposition of the material on the opposing facet, which will result in premature constriction, and formation of a void in the structure, if the process is not optimized. The redeposition probability increases as the distance between the two opposing facets decreases, hence the effects of redeposition become more prevalent as the critical dimension of the trenches decreases.
Evolving semiconductor device designs and dramatically reduced feature sizes have resulted in several applications where HDP processes are challenged in filling the high aspect ratio structures (AR>7:1) using existing technology. Historically, attempts to optimize the sputter:deposition (SD) ratio and the use of ambient gases which facilitate directional film growth in the trenches have been used too maximize the gap-fill capability of the HDP process. For structures at the 65 nm technology node, an active etch step, which removes material from the sidewall of the trenches, has been found to enable a void-free gap fill (see e.g., U.S. Pat. No. 6,030,881). A drawback of this process is that impurities (e.g., F, N and/or C from the chemical etchant used) are typically incorporated in the film. The problems associated with F doping are well known both for front-end and back-end applications (see, for example, T. B. Hook, et. al., IEEE Transactions on Electronic Devices, 48, 7, 1346–53, July 2001).
Accordingly, a gap fill process further optimized for high aspect ratio structures would be desirable.